From the 90 nm CMOS integrated circuit technique, Strain Channel Engineering with the purpose of enhancing carrier mobility of channel plays an increasingly important role with continuous reduction of a feature size of a device. Various strain technologies and new materials are used in the device process, that is, introducing a compressive stress or a tensile stress in the channel direction to thereby enhance the channel carrier mobility and improve the device performance.
For example, for 90 nm process node, compressive stress in a PMOS device is provided by using embedded SiGe (e-SiGe) source/drain or using a (100) crystal orientation substrate in combination with a tensile stress contact etch stop layer (tCESL); for 65 nm process node, the first generation source/drain stress memorization technique (SMT×1) is further adopted on the basis of the 90 nm process node, for example, a dual contact etch stop layer is used; for 45 nm process node, the second generation source/drain stress memorization technique (SMT×2) is used on the basis of the previous technique, for example, e-SiGe technique may be used in combination with a tCESL or a dual CESL, besides, Stress Proximity Technique (SPT) may be used, moreover, a (110)-plane substrate is adopted for PMOS and a (100)-plane substrate is adopted for NMOS; after 32 nm process node, the third generation source/drain stress memorization technique (SMT×3) is used, for example, embedded SiC source/drain is used on the basis of the previous techniques to enhance the tensile stress in an NMOS device.
Furthermore, in order to provide a carrier mobility in the channel region, various non-Si based materials, such as Ge, GaAs, InP, GaSb, InAs and InSb whose (electron) mobility is gradually increased, may be adopted.
On the other hand, in the existing sub-20 nm technology, three-dimensional multi-gate devices (FinFET or Tri-gate) become the main device structure, and such a structure enhances the gate control capability and is adaptable to manufacture a fine structure. Further, the stress is also needed to be increased in these three-dimensional multi-gate devices to thereby enhance the carrier mobility and to enhance the device performance. Generally, the stress is applied by a method of selectively epitaxially growing stress fins comprised of above mentioned high mobility materials or strained materials and used as both the source and drain regions and the channel regions, that is, global strained fins by taking the Si line formed by etching on a substrate isolation structure (e.g., SOI) as a substrate. Another method is to selectively epitaxially grow Si to form Si fins by taking the Si line formed by etching on a substrate isolation structure (e.g., SOI) as a substrate, then to selectively grow the above mentioned high-stress materials after removing the original part of Si fins from the source and drain regions to produce an effect of uni-axial strain.
However, in the aforementioned prior art, the technology of channel substrate global strained materials or high mobility substrate materials will cause more technical difficulties as compared with the mainstream uni-axial strain technology such as: the change of energy level, change of density of states, and change of carrier concentration due to change of substrate materials; the effect of growth defects of materials; the problem of matching with different strain requirements of CMOS device; and the problem of compatibility with the mainstream HK/MG.